Transistor sizing for low power CMOS circuits

This publication has 15 references indexed in Scilit:

• Reducing power dissipation in serially connected MOSFET circuits via transistor reordering
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Accurate Estimation of Combinational Circuit Activity
  Proceedings of the 39th conference on Design automation - DAC '02, 1995
• Inverter models of CMOS gates for supply current and delay evaluation
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
• Delay analysis of series-connected MOSFET circuits
  IEEE Journal of Solid-State Circuits, 1991
• Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
• CMOS Circuit Speed and Buffer Optimization
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
• FFT scaling in Domino CMOS gates
  IEEE Journal of Solid-State Circuits, 1985
• An algorithm for CMOS timing and area optimization
  IEEE Journal of Solid-State Circuits, 1984
• Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
  IEEE Journal of Solid-State Circuits, 1984
• Delay and Power Optimization in VLSI Circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1984