The synthesis and implementation of signal processing applications specific VLSI CORDIC arrays
- 4 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 13 references indexed in Scilit:
- Analysis and modeling of sequential iterative algorithms for parallel and pipeline implementationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- From recursive algorithm to parallel VLSI accelerator: a hierarchical design system with testbedPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An optimal floating-point pipeline CMOS CORDIC processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Systolic array implementation of nested loop programsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A design methodology for fixed-size systolic arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A New Class of Parallel Algorithms for Solving Systems of Linear EquationsSIAM Journal on Scientific and Statistical Computing, 1989
- A new model for the high level description and simulation of VLSI networksPublished by Association for Computing Machinery (ACM) ,1989
- Design and VLSI Implementation of a Concurrent Solver for N-Coupled Least-Squares Fitting ProblemsIEEE Journal on Selected Areas in Communications, 1986
- A Cordic Arithmetic Processor ChipIEEE Transactions on Computers, 1980
- A unified algorithm for elementary functionsPublished by Association for Computing Machinery (ACM) ,1971