Reliability- and Process-variation aware design of integrated circuits — A broader perspective
- 1 April 2011
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 15417026,p. 4A.1.1-4A.1.11
- https://doi.org/10.1109/irps.2011.5784500
Abstract
A broad review the literature for Reliability- and Process-variation aware VLSI design shows a re-emergence of the topic as a core area of active research. Design of reliable circuits with unreliable components has been a challenge since the early days of electro-mechanical switches and have been addressed by elegant coding and redundancy techniques. And radiation hard design principles have been used extensively for systems affected by soft transient errors. Additional modern reliability concerns associated with parametric degradation of NBTI and soft-broken gate dielectrics and proliferation of memory and thin-film technologies add new dimension to reliability-aware design. Taken together, these device, circuit, architectural, and software based fault-tolerant approaches have enabled continued scaling of integrated circuits and is likely to be a part of any reliability qualification protocol for future technology generations.Keywords
This publication has 54 references indexed in Scilit:
- On the possibility of degradation-free field effect transistorsApplied Physics Letters, 2008
- Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and DegradationIEEE Micro, 2005
- Physical limits of silicon transistors and circuitsReports on Progress in Physics, 2005
- Toward Hardware-Redundant, Fault-Tolerant Logic for NanoelectronicsIEEE Design & Test of Computers, 2005
- The impact of intrinsic device fluctuations on CMOS SRAM cell stabilityIEEE Journal of Solid-State Circuits, 2001
- Fast and exact simultaneous gate and wire sizing by Lagrangian relaxationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999
- A Defect-Tolerant Computer Architecture: Opportunities for NanotechnologyScience, 1998
- Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation studyIEEE Transactions on Electron Devices, 1998
- Upset hardened memory design for submicron CMOS technologyIEEE Transactions on Nuclear Science, 1996
- A tutorial on built-in self-test. I. PrinciplesIEEE Design & Test of Computers, 1993