Upset hardened memory design for submicron CMOS technology
- 1 December 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 43 (6) , 2874-2878
- https://doi.org/10.1109/23.556880
Abstract
A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technologyKeywords
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