Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments
- 1 January 1995
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 45-53
- https://doi.org/10.1109/test.1995.529816
Abstract
This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction.Keywords
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