Test scheduling for high performance VLSI system implementations

6 January 2003

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 421-430
https://doi.org/10.1109/test.1988.207829

Abstract

Advances in VLSI technologies permit the implementation of complex computers on a single chip. Testing high performance VLSI systems containing pipelines and multifunctional units is a formidable task due to the complexity of the implementations. One of the most important problems facing test designers is the time required to perform satisfactory testing. Exploiting the potential testing parallelism is essential for reducing the total test time. Previous work in test scheduling dealt with single aspects of test parallelism. In this paper, a broader modeling foundation that encompasses both dimensions, space and time, of the test parallelism space is introduced. A powerful suboptimum heuristic for scheduling tests on general purpose high performance VLSI system implementations is presented. The scheduling algorithm has been implemented and performance results are presented.

Keywords

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