Analysis of resistive bridging fault detection in BiCMOS digital ICs
- 1 September 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 1 (3) , 342-355
- https://doi.org/10.1109/92.238451
Abstract
This paper presents a study of the effects on the electrical behavior of BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the static and dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering different testing techniques (current monitoring, functional, and delay testing). Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection of bridging faults in BiCMOS circuits is more difficult than in the CMOS case when functional or delay testing is used whereas it becomes more effective when adopting current monitoring.Keywords
This publication has 27 references indexed in Scilit:
- A new BiCMOS/CMOS gate comparison/design methodology and supply voltage scaling modelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Fault simulation and test pattern generation at the multiple-valued switch levelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- On the detection of delay faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Detecting bridging faults with stuck-at test setsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- On computing the sizes of detected delay faultsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- A statistical model for delay-fault testingIEEE Design & Test of Computers, 1989
- Influence of device parameters on the switching speed of BiCMOS buffersIEEE Journal of Solid-State Circuits, 1989
- Fault and error models for VLSIProceedings of the IEEE, 1986
- Test Considerations for Gate Oxide Shorts in CMOS ICsIEEE Design & Test of Computers, 1986
- Inductive Fault Analysis of MOS Integrated CircuitsIEEE Design & Test of Computers, 1985