A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity
- 1 November 2009
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A PCI Express 2.0/1.0 compatible SERDES system had been fabricated in TSMC 40 nm CMOS technology. With the implementation of one lane transceiver, PLL, and PCS, the experimental results have shown this test chip passes PCI Express 2.0/1.0 TX compliance test and RX compliance test. It also achieves receiver jitter tolerance up to 0.33UI at BER of 10 -12 with stressing all spec. specified jitter sources. A compact area of 510 um * 710 um for one lane has been achieved while consuming only 125 mW from 0.9 V supply.Keywords
This publication has 6 references indexed in Scilit:
- A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS TechnologyIEEE Journal of Solid-State Circuits, 2006
- A 25-Gb/s CDR in 90-nm CMOS for High-Density InterconnectsIEEE Journal of Solid-State Circuits, 2006
- A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS TechnologyIEEE Journal of Solid-State Circuits, 2006
- A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalizationIEEE Journal of Solid-State Circuits, 2005
- Analysis and modeling of bang-bang clock and data recovery circuitsIEEE Journal of Solid-State Circuits, 2004
- An 84-mW 4-Gb/s clock and data recovery circuit for serial link applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002