Testability analysis and insertion for RTL circuits based on pseudorandom BIST

This publication has 10 references indexed in Scilit:

• The analysis of parallel BIST by the combined Markov chain (CMC) model
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• An easily computed functional level testability measure
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Circular BIST with partial scan
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• SYNTEST: an environment for system-level design for test
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A tutorial on built-in self-test. I. Principles
  IEEE Design & Test of Computers, 1993
• Estimating testing effectiveness of the circular self-test path technique
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
• A design for testability scheme with applications to data path synthesis
  Published by Association for Computing Machinery (ACM) ,1991
• Force-directed scheduling for the behavioral synthesis of ASICs
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
• Automated BIST for sequential logic synthesis
  IEEE Design & Test of Computers, 1988
• On using signature registers as pseudorandom pattern generators in built-in self-testing
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988