A low-overhead scheme for testing a bit-level finite ring systolic array

This publication has 15 references indexed in Scilit:

• An efficient bit-level systolic cell design for finite ring digital signal processing applications
  Journal of Signal Processing Systems, 1989
• High-speed signal processing using systolic arrays over finite rings
  IEEE Journal on Selected Areas in Communications, 1988
• A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders
  IEEE Transactions on Computers, 1987
• Use of unidirectional data flow in bit-level systolic array chips
  Electronics Letters, 1986
• Fault and error models for VLSI
  Proceedings of the IEEE, 1986
• VLSI Testing
  Computer, 1984
• The Design of Easily Testable VLSI Array Multipliers
  IEEE Transactions on Computers, 1984
• Built-In Testing of One-Dimensional Unilateral Iterative Arrays
  IEEE Transactions on Computers, 1984
• Why systolic architectures?
  Computer, 1982
• A Testable Design of Iterative Logic Arrays
  IEEE Transactions on Computers, 1981