CMOS Hardening Techniques

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Abstract
Complementary symmetry MOS circuits have high noise immunity and low power consumption which make them particularly suitable for military and space applications. A major drawback to their use is radiation sensitivity to accumulated fluences of radiation and also to prompt radiation bursts (transient effects). A significant degree of hardening against transient effects can be achieved by building the circuits in silicon-on-sapphire. This technology provides complete dielectric isolation and reduces photocurrents in the silicon. It is shown that each device type (N and P channel) must operate under both negative and positive gate bias. Therefore, to ensure hardening against an accumulated fluence of radiation, a dielectric which is hard under both polarities of gate bias should be used. Results are presented for CMOS circuits made with Al2O3 gate insulators.

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