SiGe:C BiCMOS technology with 3.6 ps gate delay
- 22 March 2004
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 5.3.1-5.3.4
- https://doi.org/10.1109/iedm.2003.1269180
Abstract
A high-speed SiGe:C HBT technology is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base-collector capacitance. A ring oscillator delay of 3.6 ps per stage was achieved. To our knowledge, this is the shortest gate delay reported to date for a SiGe technology. The HBTs demonstrate an f/sub T/ of 190 GHz, an f/sub max/ of 243 GHz, and a BV/sub CEO/ of 1.9 V at an drawn emitter size of 0.175/spl times/0.84 /spl mu/m/sup 2/. The high-speed HBT module has been integrated in a 0.25 /spl mu/m CMOS platform.Keywords
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