Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling
- 1 November 1991
- journal article
- Published by Springer Nature in Journal of Electronic Testing
- Vol. 2 (4) , 351-372
- https://doi.org/10.1007/bf00135230
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- Computational complexity of controllability/observability problems for combinational circuitsIEEE Transactions on Computers, 1990
- On the C-Testability of Generalized CountersIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- C-Testability of Two-Dimensional Iterative ArraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- The Design of Easily Testable VLSI Array MultipliersIEEE Transactions on Computers, 1984
- Built-In Testing of One-Dimensional Unilateral Iterative ArraysIEEE Transactions on Computers, 1984
- Verification Testing—A Pseudoexhaustive Test TechniqueIEEE Transactions on Computers, 1984
- Design for Autonomous TestIEEE Transactions on Computers, 1981
- Design of Easily Testable Bit-Sliced SystemsIEEE Transactions on Computers, 1981
- A Testable Design of Iterative Logic ArraysIEEE Transactions on Computers, 1981
- Fault Detection in Iterative Logic ArraysIEEE Transactions on Computers, 1971