Design considerations for CMOS near the limits of scaling
- 1 March 2002
- journal article
- Published by Elsevier in Solid-State Electronics
- Vol. 46 (3) , 315-320
- https://doi.org/10.1016/s0038-1101(01)00102-2
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Future prospects for Si CMOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Monte Carlo modeling of threshold variation due to dopant fluctuationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Reliability projection for ultra-thin oxides at low voltagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 25 nm CMOS design considerationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Nanoscale CMOSProceedings of the IEEE, 1999
- Generalized scale length for two-dimensional effects in MOSFETsIEEE Electron Device Letters, 1998
- Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET'sIEEE Electron Device Letters, 1997
- Supply and threshold voltage optimization for low power designPublished by Association for Computing Machinery (ACM) ,1997