A general proof for overlapped multiple-bit scanning multiplications
- 1 February 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 38 (2) , 172-183
- https://doi.org/10.1109/12.16494
Abstract
Because of recent advances in technology, multibit scanning implementations can be considered that exceed three-bit and four-bit groupings. The generalized proof for the multibit overlapped scanning multiplication is introduced, and the multiplication process is discussed. The proofs are intended to establish the correctness of the decode and the actions taken to produce the multiplication of any valid scheme proposed in the past, and to dictate the correct decode and actions taken for any overlapped s-bit scanning algorithm such that s is a natural number greater than or equal to two. The multiplication is considered to be between two fractional numbers, which are represented in two's-complement form.Keywords
This publication has 10 references indexed in Scilit:
- Quasi-Universal VLSI Multiplier with Signed Digit ArithmeticPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A high-speed multiplier using a redundant binary adder treeIEEE Journal of Solid-State Circuits, 1987
- High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition TreeIEEE Transactions on Computers, 1985
- Composite Parallel CountersIEEE Transactions on Computers, 1980
- A Compact High-Speed Parallel Multiplication SchemeIEEE Transactions on Computers, 1977
- A Proof of the Modified Booth's Algorithm for MultiplicationIEEE Transactions on Computers, 1975
- Fast MultipliersIEEE Transactions on Computers, 1970
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964
- High-Speed Arithmetic in Binary ComputersProceedings of the IRE, 1961
- A SIGNED BINARY MULTIPLICATION TECHNIQUEThe Quarterly Journal of Mechanics and Applied Mathematics, 1951