Combined topological and functionality based delay estimation using at layout-driven approach for high level applications
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- Early matching of system requirements and package capabilitiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Accurate prediction of physical design characteristics for random logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A new area and shape function estimation technique for VLSI layoutsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- TELE: a timing evaluator using layout estimation for high level applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- FPD-an environment for exact timing analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- LAST: a layout area and shape function estimator for high level applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Layout driven technology mappingPublished by Association for Computing Machinery (ACM) ,1991
- Techniques for area estimation of VLSI layoutsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- On a Pin Versus Block Relationship For Partitions of Logic GraphsIEEE Transactions on Computers, 1971
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966