Testing combinational iterative logic arrays for realistic faults
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- Easily testable iterative unidimensional CMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Testing iterative logic arrays for sequential faults with a constant number of patternsIEEE Transactions on Computers, 1994
- Improving the theory of truth table verification of iterative logic arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Test generation for iterative logic arrays based on an N-cube of cell states modelIEEE Transactions on Computers, 1991
- Hierarchical test generation using precomputed tests for modulesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Testing and Reliable Design of CMOS CircuitsPublished by Springer Nature ,1990
- C-Testability of Two-Dimensional Iterative ArraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- A Testable Design of Iterative Logic ArraysIEEE Transactions on Computers, 1981
- Truth-Table Verification of an Iterative Logic ArrayIEEE Transactions on Computers, 1976
- Tessellation Aspect of Combinational Cellular Array TestingIEEE Transactions on Computers, 1974