Path-delay-fault testability properties of multiplexor-based networks
- 31 July 1993
- journal article
- Published by Elsevier in Integration
- Vol. 15 (1) , 1-23
- https://doi.org/10.1016/0167-9260(93)90002-t
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Synthesis of robust delay-fault-testable circuits: practiceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- On properties of algebraic transformations and the synthesis of multifault-irredundant circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Synthesis of robust delay-fault-testable circuits: theoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Is redundancy necessary to reduce delay?IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplicationIEEE Transactions on Computers, 1991
- Design of robustly testable combinational logic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic NetsIEEE Transactions on Electronic Computers, 1966