Fault detection and design complexity in C-testable VLSI arrays
- 1 January 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 39 (12) , 1477-1481
- https://doi.org/10.1109/12.61070
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labelingJournal of Electronic Testing, 1991
- Invited Paper A C-testability approach for two dimensional iterative arrays†International Journal of Electronics, 1988
- Testability Conditions for Bilateral Arrays of Combinational CellsIEEE Transactions on Computers, 1986
- Built-In Testing of One-Dimensional Unilateral Iterative ArraysIEEE Transactions on Computers, 1984
- A Testable Design of Iterative Logic ArraysIEEE Transactions on Computers, 1981
- A Functional Approach to Testing Bit-Sliced MicroprocessorsIEEE Transactions on Computers, 1981
- Fault Detection in Bilateral Arrays of Combinational CellsIEEE Transactions on Computers, 1978
- Testable Sequential Cellular ArraysIEEE Transactions on Computers, 1976
- Multiple Fault Detection in Arrays of Combinational CellsIEEE Transactions on Computers, 1975
- Easily Testable Iterative SystemsIEEE Transactions on Computers, 1973