Zero skew clock routing with minimum wirelength
- 1 January 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
- Vol. 39 (11) , 799-814
- https://doi.org/10.1109/82.204128
Abstract
No abstract availableKeywords
This publication has 18 references indexed in Scilit:
- Zero-skew clock routing trees with minimum wirelengthPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Clock routing for high-performance ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A clock net reassignment algorithm using Voronoi diagramPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Three-dimensional routing for multilayer ceramic printed circuit boardsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- High-performance clock routing based on recursive geometric matchingPublished by Association for Computing Machinery (ACM) ,1991
- Clock skew optimizationIEEE Transactions on Computers, 1990
- High performance clock distribution for CMOS ASICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- Synchronizing Large Systolic ArraysPublished by SPIE-Intl Soc Optical Eng ,1982
- The Rectilinear Steiner Tree Problem is $NP$-CompleteSIAM Journal on Applied Mathematics, 1977
- The Transient Response of Damped Linear Networks with Particular Regard to Wideband AmplifiersJournal of Applied Physics, 1948