Interface properties of passivated HgZnTe

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Abstract
Reports the results of C-V measurements performed on several metal/insulator/HgZnTe structures in which the insulator/HgZnTe interface is treated according to different passivation processes. The first passivation process corresponds to the deposition of a dielectric layer (ZnS or SiO) on an etched HgZnTe surface. For the second process, a native oxide film is grown anodically starting from the electroetched HgZnTe surface in an electrochemical cell. Two different basic electrolysis solutions (KOH and C4H13NO) are used. The interface properties are determined directly from the C-V experiment at 90 K. The flat-band voltage occurs at a negative bias for all process and MIS devices have a relatively low concentration of positive fixed surface charge density going from 2*1010 to 3*1011 cm-2. The narrow hysteresis in the capacitance-voltage characteristics indicates the presence of slow trapping effects. Temperature-aging experiments under bias reveal that mobile ionic charges have a negligible influence on the shift in the C-V curves. The energy density of interface states is obtained by Terman's analysis. Passivations with SiO deposition and with an anodic oxide (KOH) lead to the best electrical interface properties on the investigated samples.

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