Abstract
As devices shrink to the 0.1 /spl mu/m scale, the junction depths of the channels and source drains of CMOS reduce to a required depth of 20 to 50 nm for 1 and 4 Gbit, and 5 to 20 nm for 16 Gbit. The ultra-low energy (ULE) implants needed to provide less projected range, the reduction of thermal budget by precise RTP and a deliberate control of transient enhanced diffusion (TED) are currently vigorous development topics and are crucial steps in achieving the ultra shallow junctions. The physical viability, economics and production-worthiness of doping by ion beam implantation for these shallow junctions will be argued. This paper surveys ion implantation for the next four device generations (to 2007) which corresponds to 200 eV to 10 keV in energy spectrum. ULE methods include the use of heavier ions, controlled instantaneous beam current density, low substrate temperatures, radiation damage engineering, box profiles and source drain extensions which delay the requirement for implant energy reduction will be discussed. Analytical data is presented showing the microstructural properties of ultra-shallow layers; dose-rate becomes a particularly important parameter in controlling the diffusion character and non-linear transitions in ion channelling that limits the profile. SIMS has a limit for the low energy heavy ions and the MEIS technique is used to quantify ULE profiles. To provide economic doping by ULE ion beams new methods of beam generation, neutralisation and transport are required. Several new strategies are described.

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