Verification techniques for substrate coupling and their application to mixed-signal IC design
- 1 March 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (3) , 354-365
- https://doi.org/10.1109/4.494197
Abstract
No abstract availableKeywords
This publication has 17 references indexed in Scilit:
- LAYIN: toward a global solution for parasitic coupling modeling and visualizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analysis and simulation of substrate coupling in integrated circuitsInternational Journal of Circuit Theory and Applications, 1995
- Mixed-signal switching noise analysis using Voronoi-tessellated substrate macromodelsPublished by Association for Computing Machinery (ACM) ,1995
- Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesisIEEE Journal of Solid-State Circuits, 1994
- Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification packageAdvances in Engineering Software, 1994
- Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuitsIEEE Journal of Solid-State Circuits, 1993
- FastCap: a multipole accelerated 3-D capacitance extraction programIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- GMRES: A Generalized Minimal Residual Algorithm for Solving Nonsymmetric Linear SystemsSIAM Journal on Scientific and Statistical Computing, 1986
- Rapid solution of integral equations of classical potential theoryJournal of Computational Physics, 1985
- Chip Substrate Resistance Modeling Technique for Integrated Circuit DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984