Circuits and techniques for high-resolution measurement of on-chip power supply noise
- 25 April 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 40 (4) , 820-828
- https://doi.org/10.1109/jssc.2004.842853
Abstract
This paper presents a technique for characterizing the statistical properties and spectrum of power supply noise using only two on-chip low-throughput samplers. The samplers utilize a voltage-controlled oscillator to perform high-resolution analog-to-digital conversion with minimal hardware. The measurement system is implemented in a 0.13-/spl mu/m process along with a high-speed link transceiver. Measured results from this chip validate the accuracy of the measurement system and elucidate several aspects of power supply noise, including its cyclostationary nature.Keywords
This publication has 5 references indexed in Scilit:
- Common-mode backchannel signaling system for differential high-speed linksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiverPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- On-Die Droop Detector for Analog Sensing of Power Supply NoiseIEEE Journal of Solid-State Circuits, 2004
- A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLsIEEE Journal of Solid-State Circuits, 2003
- Stationary and cyclostationary random process modelsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002