A comparison of defect models for fault location with Iddq measurements
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1051-1060
- https://doi.org/10.1109/test.1993.470593
Abstract
Iddq testing, where quiescent current is measured for a variety of states in static CMOS circuits, has emerged as a useful fault detection technique. In this paper it is shown that Iddq tests may be used for precise diagnosis of defects, using both inter and intra-gate shorts as fault models. The effects of these models are compared, using chips from a standard cell ASIC run. Of the 151 parts in the sample, diagnoses have been obtained from 135 of them. In many of these cases, the predicted defects are confined to a single standard cell.<>Keywords
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