Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations
- 1 January 1996
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 34, 318-326
- https://doi.org/10.1109/relphy.1996.492137
Abstract
A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.Keywords
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