A block organized 64-kbit CCD memory

Abstract

Describes the design and performance of a cost effective 64K CCD memory. The memory is organized 65536/spl times/1 in 16 randomly accessible serial-parallel-serial (SOS) blocks of 4096 bits. The memory operates over a frequency range of 1 to 5 MHz and has an average latency of 410 /spl mu/s at 5 MHz. A chip size of 4.4 mm/spl times/5.8 mm (175 mil/spl times/228 mil) is achieved by interlacing the data and using the electrode per bit approach within the SPS blocks. The chip geometry permits the device to be packaged in conventional 300-mil 16-pin package offering high board density. The typical power dissipation is 220 mW L<3.5 /spl mu/W/bit) in the active mode at 5 MHz and 40 mW (<1/spl mu/W/bit) in the standby recirculate mode at 1 MHz. The device is processed with Isoplanar two-polysilicon gate n-channel technology employing buried-channel CCD structures.

Keywords

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