Opportunities for reduced power dissipation using three-dimensional integration

Abstract
The opportunities for reducing power dissipation using three-dimensional integration, particularly the power needed to switch the interconnects, are investigated. In a three- dimensional implementation, both the gate pitch and the total interconnect length in gate pitches can be reduced from the values required in a two-dimensional implementation. The simultaneous scaling of these two values leads to an overall reduction in the interconnect power by roughly a factor of the square root of the number of strata. For example, use of four strata leads to roughly a 50% reduction in total interconnect power. The reduction in interconnect lengths leads to smaller interconnect capacitances, offering the opportunity to lower transistor power as well. I. INTRODUCIION The seemingly ceaseless increase in power dissipation with technology scaling is one of the major concerns in the future advancement of microprocessor performance (I). In (I), a 2.7~ increase in dynamic transistor power every two years is projected. In addition, aggressive scaling of the threshold voltage to meet performance constraints is projected to yield even more rapid increases in leakage power. This problem is only further exacerbated by the growing demands placed on the interconnect network. Given constant relative cross- sectional dimensions, the capacitance per unit length of an interconnect remains constant as it is reduced to smaller and smaller scales (2). As the lengths of many of the on-chip interconnects, primarily those used for global communication, are increased with growing die areas, the total capacitance of those interconnects increases, requiring larger currents and wider transistors. Coupling the increasing density of interconnects with the scaling to new technology generations, the overall leakage power, and indeed the interconnect power itself, may both grow substantially. Leakage power may grow to be as large as 50% of the total power consumption of a chip (2), while interconnect power is projected to be in excess of 30% of the total power (31, (41. Repeaters have been investigated as a tool to reduce the total interconnect capacitance and show promise in this realm 131. Circuit design complexity, however, is greatly increased with the introduction of massive numbers of repeaters into a system as repeater placement and increased via blockage kcome critical issues (2). The wiring requirements of future gigascale integrated (GSI) systems are forecast as a key limiter to a chip's area, power dissipation, and performance (5)-(7). The prospect of t Ti- 2 Tis, 1

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