A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS
- 1 March 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (3) , 294-303
- https://doi.org/10.1109/4.494191
Abstract
No abstract availableKeywords
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