A satisfiability-based test generator for path delay faults in combinational circuits

This publication has 17 references indexed in Scilit:

• Efficient generation of test patterns using Boolean difference
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Equivalence of robust delay-fault and single stuck-fault test generation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Combinational circuit ATPG using binary decision diagrams
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• On the design of path delay fault testable combinational circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Design of robustly testable combinational logic circuits
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
• Random pattern testability of delay faults
  IEEE Transactions on Computers, 1988
• On Delay Fault Testing in Logic Circuits
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
• Graph-Based Algorithms for Boolean Function Manipulation
  IEEE Transactions on Computers, 1986
• An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
  IEEE Transactions on Computers, 1981
• Analyzing Errors with the Boolean Difference
  IEEE Transactions on Computers, 1968