Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
- 4 April 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 13 (4) , 427-438
- https://doi.org/10.1109/tvlsi.2004.842916
Abstract
Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.Keywords
This publication has 20 references indexed in Scilit:
- Concurrent interleaving architectures for high-throughput channel codingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Parallel VLSI architecture for MAP turbo decoderPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 80 Mb/s low-power scalable turbo codec corePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Area-efficient high-speed decoding schemes for turbo decodersIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002
- Area-efficient high speed decoding schemes for turbo/MAP decodersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A code-matched interleaver design for turbo codesIEEE Transactions on Communications, 2002
- Parallel turbo coding interleavers: avoiding collisions in accesses to storage elementsElectronics Letters, 2002
- A low latency SISO with application to broadband turbo decodingIEEE Journal on Selected Areas in Communications, 2001
- VLSI architectures for turbo codesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1999
- Optimal decoding of linear codes for minimizing symbol error rate (Corresp.)IEEE Transactions on Information Theory, 1974