A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter
- 1 January 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 33 (12) , 1920-1931
- https://doi.org/10.1109/4.735532
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOSIEEE Journal of Solid-State Circuits, 1996
- A direct-conversion receiver for 900 MHz (ISM band) spread-spectrum digital cordless telephoneIEEE Journal of Solid-State Circuits, 1996
- A 10 b, 20 Msample/s, 35 mW pipeline A/D converterIEEE Journal of Solid-State Circuits, 1995
- A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supplyIEEE Journal of Solid-State Circuits, 1995
- A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADCIEEE Journal of Solid-State Circuits, 1994
- A 15-b 1-Msample/s digitally self-calibrated pipeline ADCIEEE Journal of Solid-State Circuits, 1993
- A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOSIEEE Journal of Solid-State Circuits, 1991
- A fast-settling CMOS op amp for SC circuits with 90-dB DC gainIEEE Journal of Solid-State Circuits, 1990
- Full-speed testing of A/D convertersIEEE Journal of Solid-State Circuits, 1984
- An error-correcting 14b/20 µ s CMOS A/D converterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981