Accurate modeling and simulation of bridging faults
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 17.4/1-17.4/4
- https://doi.org/10.1109/cicc.1991.164111
Abstract
A transistor-level examination of bridging faults and the resulting logic-level bridging fault model are described. Experiments with simulations and silicon demonstrate its accuracy. It is shown how to determine the logic value resulting from a bridging fault. This leads to a novel approach for test pattern generation and fault simulation. It is pointed out that the voting model accurately describes the behavior of shorted nodes in CMOS custom digital circuits. The logic value of shorted nodes is equal to the logic value output by the circuit with the most current drive. The threat of an intermediate voltage is very slight; therefore, bridging faults result in valid logic values on the shorted nodes.Keywords
This publication has 8 references indexed in Scilit:
- Detecting bridging faults with stuck-at test setsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Diagnosing CMOS bridging faults with stuck-at fault dictionariesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Realistic fault modeling for VLSI testingPublished by Association for Computing Machinery (ACM) ,1987
- A Practical Approach to Fault Simulation and Test Generation for Bridging FaultsIEEE Transactions on Computers, 1985
- Inductive Fault Analysis of MOS Integrated CircuitsIEEE Design & Test of Computers, 1985
- Testing for Bridging Faults (Shorts) in CMOS CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Design for Autonomous TestIEEE Transactions on Computers, 1981
- Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their TestabilityIEEE Transactions on Computers, 1980