Analogue fault simulation based on layout dependent fault models
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 641-649
- https://doi.org/10.1109/test.1994.528009
Abstract
A testability analysis procedure for complex analogue circuits is presented based on layout dependent fault models extracted from process defect statistics. The technique has been applied to a mixed-signal phase locked loop circuit and a number of test methodologies have been evaluated including the existing production test. It is concluded that the fault coverage achieved by this test can be improved by the use of a supplementary test based on power supply variations.Keywords
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