Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Testing of glue logic interconnects using boundary scan architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A unified theory for designing optimal test generation and diagnosis algorithms for board interconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A new framework for analyzing test generation and diagnosis algorithms for wiring interconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Testing and diagnosis of interconnects using boundary scan architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Diagnosis for wiring interconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A framework and method for hierarchical test generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Accelerated Fault Simulation and Fault Grading in Combinational CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Diagnosis & Reliable Design of Digital SystemsPublished by Springer Nature ,1976