Variable taper CMOS buffer design
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 15 references indexed in Scilit:
- Split-capacitive load variable taper buffer designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Variable-taper CMOS buffersIEEE Journal of Solid-State Circuits, 1991
- An enhanced technique for simulating short-circuit power dissipationIEEE Journal of Solid-State Circuits, 1989
- Very large scale integrated CMOS buffer designMicroelectronics Reliability, 1989
- CMOS Circuit Speed and Buffer OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Accurate simulation of power dissipation in VLSI circuitsIEEE Journal of Solid-State Circuits, 1986
- Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuitsIEEE Journal of Solid-State Circuits, 1984
- Driving large capacitance in MOS LIS systemsIEEE Journal of Solid-State Circuits, 1984
- CMOS circuit optimizationSolid-State Electronics, 1983
- Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systemsIEEE Journal of Solid-State Circuits, 1979