Variable-taper CMOS buffers

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Abstract
A variable-taper (VT) approach to buffer design is proposed where the taper from one inverter stage to the next is a function of the position of the inverter within the buffer chain. Though the minimum delay obtained by using a VT buffer is about 15~o more than the minimum delay obtained from conven- tional fixed-taper (ET) buffers, a small modification to the initial stages of the VT buffer reduces this difference to less than 2%. For similar delays, a VT buffer usually takes less area and consumes less power than an IT buffer. w ITH the scaling down of device dimensions, the difference in capacitance of the logic circuitry and the output stages is ever increasing. Lin and Linholm (1) used a tapered chain of inverters where each inverter in the buffer chain ch-ives another inverter which is ~f times its own size. Several authors improved this model to include the no-lc~ad delays of the logic gate (2), short- circuit currents ir the signal transients (3), and the effect of the output capacitance of the driving stage (4)-(9). We propose a tapered buffer model of which the taper factor from one inverte:: stage to the next is a variable depen- dent on the local ion of the inverter in the buffer chain. Two important factors considered in the design of the buffers are the delay penalty factor l) and the area penalty factor zl. The delay penalty factor is the ratio of the propagation clelay of the buffer chain to the propaga- tion delay of a logic-level inverter. The area penalty factor is the ratio of the buffer area to the area of a logic-level inverter. In Secl.ion H, A and D are derived for a variable-taper (VT) buffer. In Section 111, the results are extended to include the self-load capacitance of the driv- ing inverter in the VT buffer design. Comparisons of power dissipations of fixed-taper (FT) and VT buffers are made in Section IV. A modification to VT buffer design that reduces the delay penalty factor of the buffer is presented in Secl ion V.

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