Split-capacitive load variable taper buffer design

This publication has 10 references indexed in Scilit:

• Variable taper CMOS buffer design
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Variable-taper CMOS buffers
  IEEE Journal of Solid-State Circuits, 1991
• CMOS tapered buffer
  IEEE Journal of Solid-State Circuits, 1990
• A module generator for optimized CMOS buffers
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
• Very large scale integrated CMOS buffer design
  Microelectronics Reliability, 1989
• CMOS Circuit Speed and Buffer Optimization
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
• Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
  IEEE Journal of Solid-State Circuits, 1984
• Optimization of device area and overall delay for CMOS VLSI designs
  Proceedings of the IEEE, 1984
• Driving large capacitance in MOS LIS systems
  IEEE Journal of Solid-State Circuits, 1984
• Comments on "An optimized output stage for MOS integrated circuits" [with reply]
  IEEE Journal of Solid-State Circuits, 1975