A small granular controlled leakage reduction system for SRAMs
- 1 November 2005
- journal article
- Published by Elsevier in Solid-State Electronics
- Vol. 49 (11) , 1776-1782
- https://doi.org/10.1016/j.sse.2005.10.020
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Experimental verification of row-by-row variable V/sub DD/ scheme reducing 95% active leakage power of SRAM'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reductionIEEE Journal of Solid-State Circuits, 2005
- Standby power reduction using dynamic voltage scaling and canary flip-flop structuresIEEE Journal of Solid-State Circuits, 2004
- A 90-nm Low-Power 32-kB Embedded SRAM With Gate Leakage Suppression Circuit for Mobile ApplicationsIEEE Journal of Solid-State Circuits, 2004
- Circuit and microarchitectural techniques for reducing cache leakage powerIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004
- Ultralow-power SRAM technologyIBM Journal of Research and Development, 2003
- Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuitsProceedings of the IEEE, 2003
- A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by currentIEEE Journal of Solid-State Circuits, 2000
- 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOSIEEE Journal of Solid-State Circuits, 1995
- Static-noise margin analysis of MOS SRAM cellsIEEE Journal of Solid-State Circuits, 1987