Scalable event routing in hierarchical neural array architecture with global synaptic connectivity
- 1 February 2010
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 21650144,p. 1-6
- https://doi.org/10.1109/cnna.2010.5430296
Abstract
An asynchronous communication scheme for scalable routing of spike events in large-scale neuromorphic hardware is presented. The routing scheme extends the Address-Event Representation (AER) protocol for spike event communication to a modular, hierarchical architecture supporting efficient implementation of global synaptic inter-connectivity across a cellular matrix of message parsing axonal relay nodes at varying spatial scales. This paper presents a probabilistic framework for analyzing trade-offs in throughput and latency of synaptic communication as a function of load and geometry, and simulation results verifying the statistics of traffic flow across the architecture.Keywords
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