Scan chain design for test time reduction in core-based ICs
Top Cited Papers
- 27 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 448-457
- https://doi.org/10.1109/test.1998.743185
Abstract
The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test applicationtime and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector setfor a high test coverage. This paper deals with the design of scan chains as transport mechanism for test patterns from IC pinsto embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number ofscan test patterns and scannable flip flops of each core. We present and analyze three scan chain architectures for core-basedICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC.Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varyingdesign parameters.Keywords
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