Extension and source/drain design for high-performance finFET devices
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- 25 June 2003
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 50 (4) , 952-958
- https://doi.org/10.1109/ted.2003.811412
Abstract
Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing different transport properties.Keywords
This publication has 8 references indexed in Scilit:
- Sub-60 nm physical gate length SOI CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A folded-channel MOSFET for deep-sub-tenth micron eraPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design analysis of thin-body silicide source/drain devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Source/drain engineering for sub-100 nm CMOS using selective epitaxial growth techniquePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Nanoscale CMOS spacer FinFET for the terabit eraIEEE Electron Device Letters, 2002
- Nanoscale CMOSProceedings of the IEEE, 1999
- Analytical threshold voltage model for short channel double-gate SOI MOSFETsIEEE Transactions on Electron Devices, 1996