Test generation for ultra-large circuits using ATPG constraints and test-pattern templates
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 13-20
- https://doi.org/10.1109/test.1996.556938
Abstract
When creating scan-based ATPG patterns: it is often necessary to constrain those patterns to satisfy certain conditions such as avoiding bus contention. A method is described that supports defining general pattern restrictions that are partitioned to allow efficient test generation.Keywords
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