Concurrent packaging architecture design
- 1 January 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B
- Vol. 18 (1) , 66-73
- https://doi.org/10.1109/96.365491
Abstract
Packaging constitutes one of the primary limits on the performance and partitioning of high density electronic systems. A concurrent design methodology for the design of physical packaging hierarchies is presented. Architecture, electrical performance, and energy management aspects of the system are included. The CAD system AUDIT implements this design methodology. The concurrent design capability has been illustrated using model systems derived from high speed Digital Equipment 3000/500 (Alpha) and IBM RS/6000 workstations. It is found that the choice of the packaging architecture as well as the impact of packaging on system performance is determined by the partitioning of the systemKeywords
This publication has 10 references indexed in Scilit:
- Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A simulation study of two-level cachesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Package architecture design and optimization tool AUDiT: Version 4.2 for inhomogeneous systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The Alpha AXP architecture and 21064 processorIEEE Micro, 1993
- Physical design alternatives for RISC workstation packagingIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1993
- Mason: A Global Floorplanning Approach for VLSI DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Optimization by Simulated AnnealingScience, 1983
- Connectivity of Random LogicIEEE Transactions on Computers, 1982
- On a Pin Versus Block Relationship For Partitions of Logic GraphsIEEE Transactions on Computers, 1971
- Transient analysis of lossless transmission linesProceedings of the IEEE, 1967