On yield consideration for the design of redundant programmable logic arrays
- 1 April 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 7 (4) , 528-535
- https://doi.org/10.1109/43.3187
Abstract
No abstract availableThis publication has 21 references indexed in Scilit:
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