Accurate delay models for digital BiCMOS

This publication has 10 references indexed in Scilit:

• Performance-driven scaling of BiCMOS technology
  IEEE Transactions on Electron Devices, 1992
• A new methodology for design of BiCMOS gates and comparison with CMOS
  IEEE Transactions on Electron Devices, 1992
• Scaling of digital BiCMOS circuits
  IEEE Journal of Solid-State Circuits, 1990
• BiCMOS gate performance optimization using a unified delay model
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1990
• Influence of device parameters on the switching speed of BiCMOS buffers
  IEEE Journal of Solid-State Circuits, 1989
• An analytical model for BiCMOS logic transient response allowing parameter variations
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1989
• Analysis and characterization of BiCMOS for high-speed digital logic
  IEEE Journal of Solid-State Circuits, 1988
• High-speed BiCMOS technology with a buried twin well structure
  IEEE Transactions on Electron Devices, 1987
• 0.5 Micron BICMOS technology
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1987
• Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects
  IEEE Transactions on Electron Devices, 1986