Performance-driven scaling of BiCMOS technology
- 1 March 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 39 (3) , 685-694
- https://doi.org/10.1109/16.123495
Abstract
A BiCMOS scaling analysis is carried out to optimize the performance of digital BiCMOS gates while accounting for the conditions that make the direct application of conventional BJT and MOS scaling rules invalid. A simple set of technological parameters that directly affect BJT and MOS device characteristics in the context of BiCMOS is identified. Scaling of the technological parameters leads to scaling of the device parameters which in turn appear in a comprehensive, accurate delay model. The scaling of logic gate delay under various possible scenarios is investigated and a set of optimal scaling rules is proposed that simultaneously scales all components of gate delay. The optimal rules require a linear reduction in horizontal and vertical dimensions, a linear increase in collector doping, and a square root reduction in supply voltage. When 1 mu m, 5 V, 8 GHz technology is scaled to 0.5 mu m, 3.5 V, 18 GHz according to the optimal scaling rules, a 2* improvement in BiCMOS performance is obtained. Despite the supply voltage reduction BiCMOS maintains a performance advantage of 1.5* over CMOS.Keywords
This publication has 12 references indexed in Scilit:
- Scaling rules for bipolar transistors in BiCMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Scaling of BiCMOS digital circuit structuresPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Future BiCMOS technology for scaled supply voltagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Low voltage performance of an advanced CMOS/BiCMOS technology featuring 18 GHz bipolar fT and sub-70 ps CMOS gate delaysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- HSST BiCMOS technology with 26 ps ECL and 45 ps 2 V CMOS inverterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A high performance 0.5 mu m BiCMOS triple polysilicon technology for 4 Mb fast SRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Accurate delay models for digital BiCMOSIEEE Transactions on Electron Devices, 1992
- 0.5 Micron BICMOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- Bipolar circuit scalingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Current gain and cutoff frequency falloff at high currentsIEEE Transactions on Electron Devices, 1969