A simultaneous placement and global routing algorithm for FPGAs
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 483-486 vol.1
- https://doi.org/10.1109/iscas.1994.408843
Abstract
An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.<>Keywords
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