A 6K-gate CMOS gate array
- 1 October 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (5) , 907-912
- https://doi.org/10.1109/JSSC.1982.1051838
Abstract
Combining advanced 2 /spl mu/m CMOS technology with a newly developed double layer metallization technology, a high-performance 6K-gate CMOS gate array has been developed, featuring an inverter propagation delay time of 0.4 ns with a power dissipation of 10 /spl mu/W/MHz/stage. As a demonstration vehicle of the high-performance gate array, a 16 bit/spl times/16 bit parallel multiplier has been designed and fabricated in which 3365 basic cells are used. Typical multiplying time has been measured to be 130 ns at a 5 MHz clock rate with a power dissipation of 275 mW.Keywords
This publication has 5 references indexed in Scilit:
- A 64Kb CMOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A bipolar 2500-gate subnanosecond masterslice LSIIEEE Journal of Solid-State Circuits, 1981
- High density CMOS processing for a 16K-bit RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- A high-speed, low-power Hi-CMOS 4K static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978
- A 16-bit LSI minicomputerIEEE Journal of Solid-State Circuits, 1976