Fixed-biased pseudorandom built-in self-test for random pattern resistant circuits
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 929-938
- https://doi.org/10.1109/test.1994.528042
Abstract
In this paper we present a new test per clock BIST technique that provides 100% fault coverage of detectable single stuck-at faults for random pattern resistant circuits with low test application time and limited hardware overhead. The technique uses selective bit-fixing plus biased pseudorandom patterns and is referred to as fixed-biased pseudorandom BIST. An automatic design tool (EBIST) specifies the necessary information for implementation of the BIST hardware. The amount of hardware overhead introduced as controlled by user specified paramefers and can therefore meet varying design specifications. Since the proposed technique relies on bit-fixing, we present a new scan cell which supports bit-fixing. Results are presented for combinational benchmark circuits and comparisons made with prior techniques with respect to test application time and hardware overhead.Keywords
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